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ADF4159 delay between Single Sawtooth Burst and TXdata

Question asked by Ivan-Rusov Employee on Oct 27, 2015
Latest reply on Nov 5, 2015 by Ivan-Rusov

Hi,

 

I have two questions.

 

1. Single Sawtooth Burst mode with external signal running is used in ADF4159.

340 ns delay is observed between TXdata edge and starting of frequency tuning. TXdata - green, Vtune - orange.

ADF4159_RAMP.PNG

PFD frequency is 100 MHz.

 

When PFD frequency decreases twice to 50 MHz the delay increases twice to 680 ns.

 

Below you can see register settings.

R7: 00100007 (TXDATA Trigger Delay, Tri Delay, Single Full Tri, Fast Ramp, Ramp Delay FL, Ramp Delay, Delayed Start Enable=Disabled; TXDATA Trigger=Enabled; Delay Clock Select=PFD CLK; 12-Bit Delay Start Word=0)

R6: 00000326 (Step Select=STEPWORD1, 20-Bit Step Word=50)

R5: 002A8F5D (TXDATA Invert, Parabolic Ramp, FSK Ramp, Dual Ramp=Disabled; TXDATA Ramp Clock=CLK DIV, Interrupt=OFF, Deviation Select=DEV WORD 1, Deviation Offset Word=5, Deviation Word=20971)

R4: 80180104 (LE SEL=LE SYNCH WITH REFIN; ?-? Modulator Mode, Ramp Status=NORMAL OPERATION; Clock Divider Mode=RAMP DIVIDER; CLK2 Divider=2; Clock Divider Select=LOAD CLK DIV 1)

R3: 01228803 (Negative Bleed Current=109.7; Negative Bleed Current, LOL, ?-? Reset=Enabled; N SEL=N WORD LOAD DELAYED 4 CYCLES; Ramp Mode=SINGLE SAWTOOTH BURST; PSK, FSK, Power-Down, CP Three-State, Counter Reset=Disabled; LDP=14 ns; PD Polarity=Negative)

R2: 0740800A (CSR, RDIV2, Reference Doubler=Disabled; Icp=2.5mA; Prescaler=8/9; R Counter=1; CLK1=1)

R1: 00000001 (Phase Adjustment=Disabled; LSB FRAC=0; Phase Value=0)

R0: B0280000 (Ramp On=Enabled; MUXOUT=DIGITAL LOCK DETECT; INT=80; MSB FRAC=0).

 

Why the delay is observed? Could the delay be removed?

 

2. Could ADF4159 generate Single/Burst Fast Ramp? In the datasheet we should write "01" in DB[11:10] in R3 which means CONTINUOS TRIANGULAR.

 

Regards,

Ivan

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