I have interfaced ADSP-533 EZ-kit with FPGA EZ-extender for investigating data read/write to the Blackfin SDRAM. According to the schemetic diagram of the both board, Address bus and Data bus of Blackfin SDRAM are contected with Blackfin-533 processor and FPGA I/O pin. But, SDRAM selection pins (CS, RAS, CAS, WE etc) are not contected with FPGA I/O pin (Though manually can be connected). In order to investigate data write/read for SDRAM of Blackfin board, FPGA needs to track CS (chip select), WE(write enable), adress bus and data bus. Noticed that Blackfin processor is running few times faster than FPGA (FPGA EZ board External Clock Frequency 25Mhz).
According to experiment, Blackfin processor holding databus and address bus data with enough time (147ns) which is enough time for FPGA read. But, Blackfin processor is providing Active low CS and WE signal with very short pulse (17.5ns) which is much more faster for FPGA to detect it.
I noticed ASYNC memory (Flash memory) can be slow down read/Write by Asynchronous memory control register. But I unable to find any method for SDRAM.
My intention to increase length of CS and WE signal time so that FPGA also can see these signals activation/deactivation.
I am looking forward to your kind suggestion.