Hello, I would like to check with you some data that is not clear for me in the documentation, together with difficulties in the lab checking.
i prefer to list first all the doubts then comment as they have some mutual relationship.
- Impossible to compensate for not so accurate OCXO clock sources
- Unvalid fPD/fSYS combinations (pg. 18 of the EVAL board doc comments on this)
- Possibility to get an Mx output with a copy of the active reference
- What means that an Mx output can deliver the system clock divided by 16
- Impossibility to obtain an accurate 1Hz output using an 1pps input
Here I call fSYS o the external clock source, not after internally multiplied to deliver the real system clock.
I checked the board for several different functionalities using different REF and SYS freqs and in all cases it worked OK except in two:
1) when the external source, even if it an OCXO, is not enough precise, even if it stable. I tried several PLL adjustments but even if it declared locked after a lot of time, the output spectral quality was unstable. In this cases, I know it will go wrong when I try a calibration and it does not converge very close to the final freq, but rather "restarts" the search, as if the SYS CLK CAL was so coarse that the system has to reset the process. This never happens when the OCXO is relatively precise (OX-221 or so), in those cases a single SYS CLK CAL attempt takes the output very close to the final result and speeds up the convergence.
In the cases I saw this, the REF was 1pps and the external clock a 10 Mhz estable source used with doubler and x50 multiplier (for 1Gs/s).
2) In one instance I was interested in testing the system with 10 MHz ref (keeping 10 MHz system input), I kept the same clock multiplier and doubler and redesigned the PLL for 10 Mhz reference. Obviously the LOCK declaration was now much sooner. It was maybe more noisy in low freq when the OCXO source was not VERY pure, but the result was very low noise again if the source is "good to very good" PN. But I observed a strange unstability appearing at relatively periodic intervals, maybe some dozens of seconds.
I reviewed many times the PLL design without success, and when i went back to my office exhausted I started to review all the doc parts that could throw light. I was surprised to remember the observations not in the data sheet but in the eval board (pg 18, "AD9548 frequency planning") preventing from using system clock frequency inputs that are equal to multiple of the phase detector frequency. I guess it means multiples of low order as if the order is 10 million as in the PPS case i guess it is irrelevant. It is true that the DDS offers flexiility to use different system frequencies and avoid these coincidence, but the designer is not always free to do so. In some cases, you are forced to the case I experienced. I wonder if the instability of the output was due to this, as it is not a slight degradation but could mean a disruption in the output clock target systems.
Concerning the Mx outputs, I would like to know: 1) if when the data sheet explais that it is possible to get in these outputs the active reference phase master it means that a copy of the selected reference will be available here, without any event that modifies its phase or ferquency in absence of switchovers, to be used as another subsystem clock without the need to multiplex the reference input prior to input to the AD9548. I mean if we are talking about a copy of the active signal or something just related for monitoring.
And 2) : when it says the Mx can deliver the system clock divided by 16, it means the internal system clock (multiplied), not the external system clock input.
Finally, just to confirm what seems apparent from the documentation, as it was deduced before testing anything: depending on the nominal output frequency, that can be a complicate rational as in my case, using an 1pps reference, it is impossible to output a 1pps output from the AD9548, as far as the divider resolution is much lower than the DDS one. It is true that in all the useful cases one is restricted to ratios that are fractional with less resolution (fractional PLL divider), and the output divider resolution (30 bit)seem to be better than the fractional divider one, but still, the system clock is to be corrected and can present an arbitrary error, that the DDS corrects with a lot of accuracy, but once you divide the output you will not have the capability to recover the original reference frequency unless you don't have the same number of bits of the DDS, not the fractional synthesizer, due to the addition of the system clock source. Is it correct? I tried for 1pps with 1Gs/s, and find that the best approximation is poor (0.95Hz). One need DIVIDER resolution to be able to get accurate, round output frequencies when the DDS is programmed for "strange" frequencies as usual in many applications.
Thanks in advance