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ADV212 VCLK Timing Requirements

Question asked by GregMefford on May 6, 2011
Latest reply on Jul 13, 2012 by DaveD

In Custom-Specific Encode Mode, does the VCLK input on the VDATA interface have to be a constant-frequency 50% duty-cycle clock, or can it essentially just be a pixel data strobe?


I'd like to be able to set the frequency to something higher than my average pixel rate and burst chunks of video data into the ADV212 in encode mode as they become available because my source material is progressive video with no blanking and I want to insert EAV/SAV blanking in the stream. I would prefer to burst the data into the ADV212 at a faster maximum rate than the source is giving it to me, which will make the buffering scheme simpler, but I couldn't find any information about whether it's OK to gate the VCLK and just strobe it for each valid pixel.