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how to configure the cplb?

Question asked by freeze on May 5, 2011
Latest reply on Jan 21, 2014 by CraigG

Now,I am using bf531.I want enable data cache memery,but I don't know how to change  the cplbtab.c.Now I show my .ldf and cplbtab.c.I hope all the people can help me.

ldf.bmp

This is my .ldf file.

 

 

 

The following is my cplbtab.c file.

#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_2_2)
#pragma diag(suppress:misra_rule_8_10)
#pragma diag(suppress:misra_rule_10_1_a)
#endif /* _MISRA_RULES */


#define CACHE_MEM_MODE CPLB_DDOCACHE_WT

 

#include <sys/platform.h>
#include <cplbtab.h>

#pragma section("cplb_data")

cplb_entry dcplbs_table[] = {


/*$VDSG<customisable-data-cplb-table>                           */
/* This code is preserved if the CPLB tables are re-generated.  */


   // L1 Data A & B, (set write-through bit to avoid 1st write exceptions)
   {0xFF800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE | CPLB_LOCK | CPLB_WT)},

   // Async Memory Bank 2 (Second)
   // Async Memory Bank 1 (Prim B)
   // Async Memory Bank 0 (Prim A)
   {0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE)},
   {0x20100000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},
   {0x20000000, (PAGE_SIZE_1MB | CACHE_MEM_MODE)},

   // 128 MB (Maximum) SDRAM memory space (32/64 MB populated on Ez-kit)
   {0x00000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_LOCK)},
   {0x00400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_LOCK)},
   {0x00800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_LOCK)},
   {0x00C00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE | CPLB_LOCK)}, 
  
   // CPLBs covering 8MB
   {0x01000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x01400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x01800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x01C00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x02C00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03000000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03400000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03800000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},
   {0x03C00000, (PAGE_SIZE_4MB | CACHE_MEM_MODE)},


   // Async Memory Bank 3
   {0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE)},

   // end of section - termination
   {0xffffffff, 0},
/*$VDSG<customisable-data-cplb-table>                           */


}; /* dcplbs_table */

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