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Help with AD9523-1 Termination design

Question asked by chintal on Oct 22, 2015
Latest reply on Oct 26, 2015 by pkern

I'm looking into using the AD9523-1 for clock distribution on a design I'm working on. I'm looking at the evaluation board gerbers, schematics, and the datasheet.

 

My application calls for a clock distribution board along the lines of the evaluation module, which takes some reference and generates various clocks at controllable (and changeable) frequencies. For the purpose of this discussion, you can assume that each clock is to be consumed by a single downstream device located on a different card two connectors away. As an example, you could assume the clock consumer is an LTC6957-3 http://cds.linear.com/docs/en/datasheet/6957fa.pdf. This IC (or perhaps some similar IC) is used to convert the AD9523-1's LVPECL/LVDS output (haven't decided which, yet) into a single ended CMOS clock for an ADC/DAC.

 

My reading of the datasheet, and whatever other reading I've done, suggest that the termination should be done close to the clock consumer, not close to the clock generator as the eval board does. I would have expected to terminate the AD9523-1's LVPECL/LVDS outputs close to the LTC6957-3 input.

 

The gerbers of the evaluation board (EVAL-AD9523-1) located at AD9523/AD9523-1 Evaluation Board | Analog Devices seem to include termination resistors and AC coupling on the eval board itself, and the traces and from there routed as 50E traces into an SMA connector.

 

How should I design my termination scheme, given the following :

 

1. AD9523-1 output should reach the consumer with as little phase noise as possible. I also hope to use the AD9523-1's Zero Delay and Phase Delay options to also minimize timing skew as far as possible.

2. I'm planning on using LVPECL/LVDS for the majority of the routing length to keep noise levels low. This clock ultimately may need conversion into a CMOS clock, for which the LTC6957-3 seems promising. I'm open to changing that to something else.

3. The duty cycle of the clock at the end should be as close to 50% as possible, so that ADC/DAC performance can be maximised.

 

The following are the specific questions that I have :

 

1. Where should the clock outputs be terminated - at the AD9523-1 or at the consumer (LTC6957-3). Note that these are on separate PCBs. Let's assume that I can maintain a 50E impedance throughout the entire signal route.

2. The AD9523-1 has too fine a pitch for me to actually draw out the traces at 50E. (I'm using 4 layer 1.6mm boards with standard stackup, meaning 50E traces are about 18-20mils wide. How would I match the impedance of the traces as they exit the IC to the longer traces which have relatively better impedance control.

3. If termination is located alongside the AD9523-1, would a second termination at the clock consumer be necessary / sustainable? The LTC6957 probably needs the clock to be AC coupled, as would most ADCs that I'm considering. I doubt the input biasing mechanism these ICs use would hold up if the AC coupling is located about 8 inches away (electrically) and through two connectors.

4. As an aside, the gerbers for EVAL-AD9523-1 show two decoupling capacitors on each supply line, one each on the solder side and the component side. Are two really necessary? Why does the schematic note "Only for AD9523" on the page for decoupling capacitors? Does the "AD9523-1" not require decoupling? What's changed?

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