I plan on using the AD8231 in a wearable application. However, my PCB fabricator has laid down minimum spacing constraint as 6 mils. The footprint of AD8231 extracted from its .bxl file shows a square copper etch region on the top layer (for the exposed pad beneath the IC); and the spacing between the IC leads and this centre etch is about 4 mils.
To resolve this conflict, I would like to increase the (pad to centre-etch) spacing on all four sides to 6 mils, by reducing the size of the centre copper etch by 2 mils on all four sides. i.e. my requirement is to reduce the original size of the centre copper etch from 90 mils x 90 mils to a slightly smaller 86 mils x 86 mils.
Will there be any issue (performance or otherwise) if I do this?