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AD9361 CLK inputs drIven by an AD9548

Question asked by HankZ on Oct 20, 2015
Latest reply on Oct 20, 2015 by tlili

According to the AD9361 datasheet (pg. 19), if an external clock is used it needs to be applied to the XTALN pin. This implies that it must be a single-ended clock and the LVDS and LVPECL options are not available.


What I would like to know is how to use the AD9548 clock buffer’s LVCMOS 1.8V outputs and drive the AD9361. The issue being that the AD9361 max input is 1.3VPP. Can you suggested a scheme to reduce the 1.8V outputs to 1.3VPP?