We're wrestling with a sideband spur issue we believe is being generated internally by the HMC833. Our external reference frequency is 112MHz. We're seeing a sideband spur around -85dBm at 140 MHz (5 x 28MHz, 20 x 7MHz, etc.) when using the output divider of the chip (1120MHz). 140Mhz just so happens to be the center of our IF and the spur manifests itself as a center spur in our system. We operate the chip in integer-only mode.
We suspect an auto-calibration counter harmonic is bleeding into the chip's output signal. We've tried varying the FSM clock with only marginal improvement (a few dB). We've tried to disable the auto-calibration by flipping the "Bypass VCO Tuning" bit (0x0A bit 11) after locking the PLL, but it doesn't help. Is there a better way to disable the auto-calibration counters? Are there other sources of ref. clock harmonics in the chip that we need to consider?
We're also looking for other ideas on how to reduce these sideband spurs.