I couldn't receive reply.
So I copy this as new discussion.
It is difficult for us to understand AD5696R I2C READ operation on figure 51.
Because all of the ACT by MASTER.
I would like to confirm a thing. Is it possible for you to check?
I think CPU should be master, DAC should be slave.
During READ OPERATION, master and slave are changed.
According to the timing chart of P22 on the datasheet of AD5696R,
Start is Master, All of the ACK are master,
Repeated start is Master, Stop is also master.
At least, Ack should be supported by receiver for data transmitter.
Phase Data Tramsmitted By ACK Trasmitted By
Start CPU -
FRAME 1 SLAVE ADDRESS CPU AD5696R?
FRAME 2 COMMAND BYTE CPU AD5696R?
FRAME 3 SLAVE ADDRESS CPU? AD5696R?
FRAME 4 MOST SIGNIFICANTDATA BYTE n AD5696R? CPU?
FRAME 5 SLAVE ADDRESS SIGNIFICANT DATA BYTE n AD5696R? CPU?
FRAME 6 MOST SIGNIFICANTDATA BYTE n – 1 AD5696R? CPU?
Stop CPU -
On the timing chart, which output Ack from CPU or AD5696R?
Or can we refer to AD5696 datasheet?
How does customer set for "FRAME 2 COMMAND BYTE"?
It seems to set internal pointer. But we couldn't find out format.
FRAME4(MSB) and FRAME6(LSB) are data?
Does FRAME 5 show address?
Should the customer confirm it same as FRAME3？