We have a problem with the encoder.
We are running in non-standard video mode (datasheet revision B),
Trying to play STANAG 3350 Class A (875i).
We are providing the encoder a 32.938MHz clock and sampling the video data DDR.
VSYNC is tied to ground.
Hsync provides all the sync data as needed in the STANAG 3350 class A specification.
The encoder outputs analog data with ringing (left circle) and glitches (right circle).
The glitch in the right cycle is ~50ns. (more than pixel time).
We tried to fix it using the undershoot limiter option (register 0x32, bit 6-5) and that solves the problem, but it affects the sync times.
In addition, could you explain the role of the C_comp, connected to the pin "COMP" pin (ADV7393).
Could you disclose the internal IC scheme to understand the influence of this CAP value to the signal? Why its value must be 2.2nF?
We are playing with this cap value now and see that the shape of the signal is changed. Would like to understand why.