In my system I have an external signal that generates a pulse every 100us, connected to the NMI input pin of a BF607.
I notice a latency of 1000ns between the falling edge of the incoming NMI trigger and the first line of code within the NMI ISR. (which is an IO pin toggle)
For the BF607 an IO pin toggle delay of approx 180ns seems to be normal due to the MMR.
To me an expected NMI ISR latency will be around 200ns.
Leaving approx 600 unexplained nano seconds left.
My cclk is running at 500MHz, only one core is used, no further interrupts running.
I checked the core timer: generates ticks every 2ns. So the core runs at 500MHz.
The following code is used:
r0 = sp;
sp += -12;
sp += 12;
*pPORTB_DATA_TGL = DebugPin4;
|bfin_write_SEC_CSTAT0(0x00010000);||// clear nmi bit|
(EVT2 is loaded with the address of Do_Code during init)
The SAVE_ALL_SYS contains ca 40 instructions, so let's say 100 instructions around the function Do_Code. With 2ns/instruction this would be 200ns.
Anyone that can explain why it takes 600ns extra?
Thanks in advance.