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AD9361 : 180° phase between two measures with external LO.

Question asked by lukronos on Oct 19, 2015
Latest reply on Oct 21, 2015 by rgetz

Hello all,

 

I am working with a FMCOMMS5 evaluation board with a zc702. I have an issue for my application.

 

I use an external LO (it is important for my application). When I do some measures consecutively I have no problem.


My issue comes when I restart the FPGA board or when I change my LO frequency then come back to my first frequency.


This issue is : when I do these actions, the adc_data bus could have two sort of results. A word, or the reversed word. For instance I do a measure and adc_data_i0 receives 010101110011 and adc_data_q0 101011101010. Then I restart the FPGA and do a new measure with adc_data_i0 receiving 101010001100 and adc_data_q0 receiving 010100010101.


When I translate these binary words to decimal, it is like I have a 180° phase between the two measures. But it is not happened each time I do these handlings, sometimes I have the same word. This behaviour is random.


So I have some questions for solving this problem :


1/ Do you know what could be the root of my issue?

2/ What can I do to have tha same behaviour each time I turn off then turn on my FPGA board?


Excuse me for my english.


Thanks you in advance.

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