Hi,

Which tool can I use to design the loop filter for AD9858 (DDS with integrated mixer and PFD)?

I'm currently evaluating AD9858 in translational loop. I want to modify the loop filter in the evaluation board, but I dont find AD9858 in ADISimPLL or ADISimCLK.

Regards,

Vishnu

Hi,

A few thoughts since you require an active loop filter.

Since the PLL feedback is unity, the PFD will see the entire 200MHz transition.

This will force the loop into cycle slipping, which will cause an extended loop settling time.

For these cases the AD9858 had some fast locking logic which forced a rapid charge up of the Zero capacitor.

For this mode the configuration in

Figure 29 of the data sheetneeds to be used.This was all intended for passive loop filter configurations.

You mention you need to use a active filter (Due to the large supply voltage and tuning range of the VCO).

So I am not sure that the fast locking logic can be effectively used with an active loop filter.

Do you have a active loop filter topology in mind?

Also, just so I get an understanding of what you need, do you know how to

design a standard passive loop filter to attain a given loop bandwidth?

Here is the method and some values for using the fast-lock logic.

The overall settling time will consist of the open loop charging time (Frequency detect mode) and then the closed loop settling time (final closed loop mode).

I suggest that you go straight from the frequency detect mode to the final closed loop mode to start

(Referencing fast Locking Logic section of data sheet).

The first step is to calculate the Zero capacitor (Cz)taking into account the amount of voltage that needs to charge.

I this case we have 200MHz/60MHz or about 3.3V. Using I=C dv/dt, we calculate the Cz capacitor value using a setting of the Frequency Detect Mode charge pump current CFR[31:30] Table 7.

For setting 11 the charge current will be about 60*(500ua)=30ma.

For a dv/dt of 3.3V/8us (8us chosen as approximate initial charge time), the C required is [(20ma)*(8us)]/3.3=72nf

(you may need to round to standard cap value)

Now you can calculate the closed loop bandwidth using the Cz calculated above.

For 400kHz loop bandwidth, I get a Rz of about 80 ohms.

(Note: For your conditions I needed to use the full 30ma Frequency Detect current to make the Cz large as possible to reduce the zero frequency for stability, while still getting the bandwidth.)

For the first ripple capacitor you can size as needed to handle reference sidebands etc.

The settings above are a good starting point for configuring the loop filter.

Depending on the switchover from the Frequency detect mode to the final loop bandwidth, you may need

to play around with the settings to optimize.

For reference Cz is the same as C2 in Figure 29 of the data sheet.

On the AD9858 translation loop evaluation board schematic, Cz is C4.

In this schematic R5 and R38 can be ignored in terms of calculating the loop filter components.

That is they can be treated as a short circuit or zero ohms.

The reason for this is that looking back into pin 64 and 65,66 there is a very high impedance(Current source outputs).

Looking back into the part from the terminals of R40, the impedance doesn’t change, it still looks like a current source.

The purpose of R50 and R5 is to dampen switching characteristics thought during the fast lock process.

They effectively isolate the internal bond wire inductance from the output capacitance.

So comparing the components on the eval board to Figure 29 data sheet.

C4 (eval bd.)=C2(fig 29)

R40(eval bd.)=R2(fig 29)