Is HIPI the same thing as using two DMA channels?
My impression was that HIPI mode is where a set of pixels or chunk of JP2K code are written to, or read from, a register in normal host mode (which is slow).
Is it also possible to configure DMA channel 0 to burst raw pixel data in and DMA channel 1 to pull JP2K compressed data out of an ADV212 in encode mode? It seems like this could be set up to be very fast (50MHz x 32 bits = 1600Mbps total burst rate if you have a 32-bit interface, half that for 16-bit).
If this is possible, is blanking still required or do the same limitations apply that apply to the RAW Pixel interface? Is this just a bad idea?
Presumably the average throughput limitation would still be 65Msamples/sec for pixel input and 200mbit/sec for compressed output assuming a 150MHz JCLK and lossy compression.
For my application, I'm not worried about buffering the video for burst DMA instead of streaming pixels because I already have the video in raster-scan packets in an FPGA anyway.