Does the latency from DAC digital input to analog output vary from power on to power on? Why?
The nature of DAC latency variation depends on its digital input structure and clock generation block structure.
Digital input structures with a FIFO typically introduce a latency variation up to the total depth of the FIFO. Upon power on, the FIFO status is unknown and thus the latency from the write pointer to read pointer of the FIFO, which is part of the total DAC latency, is unknown. By resetting the FIFO to a certain depth, this latency variation can be removed.
There is another inherent variation from the clock generation block. Since some of the clocks in a DAC, especially those with signal processing, run at slower speeds, compared to the DAC clock, usually at sub-multiple rates of the DACCLK, there is phase uncertainty in these slower (divided down) clocks, which introduces latency variations at the DAC output. This variation can be removed by using the synchronization feature in the DAC.
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