We plan to use several DDS (let's say 10) in one system.
All the DDS get the same profiles.
All the DDS get the same REF_CLK of 100Mhz via a CXO and a clock distribution device, all adjusted for 0 delay /squew between them. The Internal PLL is used and operating at 2.5Ghz.
When switching off the power of the DDS only and then switching ON:
1- Will each DDS return to its previous frequency, Phase and amplitude (profiles are saved) after each switch ON?
2- Will we see a difference between the 10 DDS after each swith OFF/ON?
3-4 Same question in case of using an external REF_CLK of 3.5Ghz (PLL is deactivated).
5-In addition, I cannot find any reference design using the SYNC_IN and SYNC_OUT for multi chip use. Can you pls send it?
6-Is it possible to route the PLL output to an external pin?