Anyone can help me on this.
The status register read back 0x80 all the time even though I put in the continue conversion mode.
The ADC data from register 0x2 never change.
Apologies for the delay. When continuous conversion mode is selected, the adc will convert continuously and the /RDY bit on the status register will go low each time a conversion is available. How often do you read the status register? Also, with /CS pin low, can you monitor the DOUT//RDY pin with a scope? You should be able to see the DOUT//RDY pin pulsing low each time a conversion is available. This is to check that the part is converting properly.
You can then read the contents of the data register after the /RDY bit or the DOUT//RDY pin go low by writing to the communications register, indicating that the next operation is a read of the data register. You must also ensure that the data register is not being accessed at the completion of the next conversion; otherwise the new conversion word is lost. Can you share the steps that you did to get the data from the adc?
Sorry for the late reply. I was on the business trip.
Do you know why I have to wait for 350ms on the ADC status bit before I can read ADC data. It doesn't sound right for the ADC to take long to complete the conversion. Any though on this?
I noticed that you placed the code for setting the channels on your main while loop, what will happen is that every time this code is executed, the ADC will interpret it as a channel change. When a channel change occurs, the modulator and filter are reset and an extra settling time is allowed to generate the first conversion. The settling time for sinc4 filter is calculated using the equation below,
tSETTLE = (4 x 32 x FS[10:0] + Dead Time)/fCLK
With you current settings,
fCLK = 153.6 kHz (mid power)
FS[10:0] = 384 (0x180)
Dead Time = 94 (FS[10:0] >=1)
you will have a settling time of about 320.61 ms which is close the 350 ms that you are getting. I would suggest that you set the channel outside the main while loop to avoid the extra settling time. I would also suggest that you set the channels first and set the control register last before you start the main loop to read the data.
Here is a link for the AD7124 No-OS software which you can use as a reference.
I put the code outside the loop. I come down to 50mS to get stable data.
Can I go to 10-20mS to acquire the data? It seem I can't go further for the stable data.
Am I setup up correctly for the single channel mode?
With your current settings (sinc3 filter, full power mode, single_cycle = 1, FS[10:0] = 2), using the equation,
fADC=fCLK/(3 x 32 x FS[10:0]) (page 56 of the datasheet)
fADC will be equal to 3200 kSPS, the ADC should be able to output a stable data every 312.5 us. I would suggest that you monitor the /RDY bit in the status register in you main while loop and read the contents of the data register after the /RDY bit goes low. This is to make sure that you are not adding extra delay on getting the data.
I would also recommend that you follow the suggested ADC configuration flow shown on Figure 68, page 39 of the datasheet.
Retrieving data ...