Hello, my group and I are working with the AD-FMCOMMS5-EBZ Evaluation Board and having issues with the synchronization between the two on-board AD9361s. We are getting sporadic valid data through our FPGA pipeline, sometimes values are doubled, or dropped completely.
Upon inspection with hardware manager debugging, we see that valid signal coming from the FMCOMMS5 board sends two valid pulses, one shortly after the first, or a single valid stretched in time to double length. After multiple restarts, we sometimes, rarely, see the valid signal aligned and outputting correctly, but it is anything but consistent.
We've created a temporary fix for our system by sampling the valid and masking, but we would like to figure out the issue from the de-sync between the AD9361s. We are sampling on the clock feeding the AD9361s on the FMCOMMS5 board during the debugging, so we don't believe that it's a false positive, especially considering the sporadic data and the masking fix. Has anyone run into this issue before?