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ADV7441A failure mode: power-up/down

Question asked by rsmillar on May 2, 2011
Latest reply on May 11, 2011 by GuenterL



We are observing a strange failure mode with the ADV7441A, described as follows:



-          ADV7441A section implemented per ADI reference design suggestions and previous communication with factory (schematic available as needed)

-          analog signal with separate H- and V-sync inputs

-          part running in open air, not "hot" or "cold"

-          when failure occurs, mode persists across power down/up cycles (more below).



The failure mode may be described as "the ADV7441A is unresponsive to all inputs including reset and produces no coherent outputs."


This failure only appears with analog signal applied and during a power down/up sequence - that is, the unit is operating normally and main power to the system is interrupted for a few seconds.  Once in this failure mode, subsequent power down/up cycles have no effect: the failure mode persists across power cycles.  The amount of time main power is removed from the system appears to be of no consequence: it may be left off for minutes and when re-applied, the failure remains.


The power-supply sequencing shown on pg. 311 of the “Hardware Database Manual” revision J (June 2010) seems to be saying that the 1.8V supplies should all be up near 1.8V before the 3.3V supply is powered-on.  We have verified that we meet this requirement by a large margin (~10ms).


Note that in a related thread on EngineerZone (topic 23376), a significantly different plan is described:


I believe that as long as the 3.3V does not exceed the 1.8V before the 1.8V is stable then everything should be OK.  The same applies in the power down sequence, the 1.8V should be stable until the 3.3V drops to 1.8V.  The reference schematic implements this functionality.


This seems to indicate that, during power-up/down of the 1.8V supplies, 3.3V should be at or less than the value of the 1.8V supply.


We have  ascertained via detailed analysis that the H- and V-sync signals from the external video source are charging the 3.3V rail through the ADI part when system power is off.  In other words, when an external (analog) video signal is applied to the device AND the device's power is OFF, the 3.3V rail remains at approximately 0.8V due to current supplied by the video source via from the H- and V-sync signals thru the ADI part.


We are concerned that this condition makes it impossible to meet the ADV7441A's unique power-down sequencing requirements and that we therefore violate that spec: that is, during power-down of the 1.8V supplies, the 3.3V rail does in fact become greater in amplitude than the 1.8V rail due to this strange “leak” of the H- and V-sync signals across the ADI part.



Has the "Sync signal current leaking thru the ADV7441A to the 3.3V supply rail" behavior been characterized by the factory?  Is this expected behavior?


As mentioned above, it appears from the datasheet's power sequence section that 3.3V supply should never be above the 1.8V supply in amplitude while the 1.8V supply is in transition (up or down).  How is this achievable given the current "bleed-through" from H- and V-sync into the 3.3V rail?


What is the expected ADV7441A behavior when this condition - 3.3V rail at 0.8V and 1.8V rail at 0V - occurs?


Thanks for your help,