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AD9361 receive FIR inherent gain

Question asked by jiezhang on Oct 13, 2015
Latest reply on Oct 13, 2015 by tlili



I'm debugging my AD9361 board, I generated a single frequency signal at 2.4G and receive by AD9361, when the code stopped before RFIR configuration in main function, the waveform captured in Artix 7 FPGA is very good and has a amplitude almost satuation. But when I added FIR filter, i.e., load FIR coeffiecents, the waveform received get worse, seems very weak, and also it was observed there is overflow from register 0x05E D0.


I am wondering what is the inherent gain in FIR module? for example, if the FIR coefficents onle have one nonzero value, others are zero and also assume there is no interpolation and decimation in FIR, fir = [0,0,0,....,0,a,0,0,0,...0], what is the value of a such that the input and output are exact same exept for a fixed delay?