Since the previous thread was labelled with correct answer, I'm wondering if my new question will reach the system. So bear with me starting a new thread.
We put our baseband TX block into the reference design project.
We set the ADC/DAC sampling rate at 60MSPS for AD9361. The clock is input to a PLL and output 60MHz and 80MHz clocks. Our TX block runs at 80MHz and output data rate is 60MSPS. We assume that tx_channel0, tx_channel1, tx_channel2, tx_channel3 are corresponding to DDS0_I, DDS0_Q, DDS1_I, DDS1_Q, and we mimic the interface for DDS0_I and DDS0_Q. Our baseband signal has a symbol rate/bandwidth 20MHz (useful bandwidth of 18MHz). So far, we haven't had luck to get it work. The spectum of the AD9361 RF output is not correct.
I think we don't have the data interface work properly. Any suggestion? Thanks.