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How to control the timing of the internal ADF4351 resync pulse

Question asked by tnjames on Oct 9, 2015
Latest reply on Oct 12, 2015 by rbrennan



I am using the ADF4351 in fractional-N mode to generate a LO for use in a receiver and I would like to be able to synchronise the time at which I retune my digital domain mixer to the phase of the LO output across retune/power cycle events.  I note that the datasheet mentions that you can use an internal phase resync pulse to ensure a repeatable input reference-to-VCO output phase relationship however whilst it would be very useful to be able to output this pulse on MUXOUT so I could then sync events in my FPGA to this pulse also this does not appear to be possible.


My question then is is it possible to force the phase of this resync signal via the SPI interface timing.  For example if I configure MUXOUT to get the output of the R counter (fPD = 25.4 MHz) I could then align rising edges on LE with the phase detector.  If I then disabled then reenabled phase resync using the clock divider mode bits in R3 and/or set the clock divider value to 0 would this then (crucially) reset and restart the internal counter used to generate the resync pulse?  If it did then I could probably regenerate a pulse with similar timing in my FPGA and then use this to trigger updates to my DDS.  Assuming this would work I have two further questions.  Does the phase resync also reset the output dividers (presumably if it doesn't the whole thing is pointless if not using the VCO output in its fundamental mode)?  Is there any guidance available re the timing relationship I need to achieve between rising edges on LE and rising edges on the R output observed on MUXOUT so I can be confident about when my changes take effect?


Thanks in advance