What is the difference between the peak current mode and the emulated peak current mode control methods?
In Peak current mode control, the power switch turns on at the beginning of each clock cycle and the inductor current ramps up. The inductor current ramp is converted to voltage and compared against the output of the error amplifier (COMP). When the ramp voltage exceeds the COMP voltage, the power switch is turned off. So, essentially, the error amplifier regulates the output voltage by regulating the inductor current.
In Emulated peak current mode coontrol, the power switch is turned on at the beginning of each clock cycle - same as the peak current mode cotrol. Instead of sensing the inductor current ramp directly and converting to voltage, an image of such a ramp is created by charging a capacitor from a current source to get an equivalent ramp during ON time. As before, when the ramp voltage exceeds the COMP voltage, the power switch is turned off. During the OFF portion of the cycle, the inductor current is sensed and fed to the same comparator input. Hence, when the next clock cycle starts, the valley current of the inductor is the starting point for the emulated ramp voltage.
The advantages of emulated current mode control:
1) Since no current sense done during Ton, there is no need for high side current sense amplifier - a design challenge
2) Emulated ramp is actually a voltage across capacitor and not output of an amplifier, so there is not settling time oscillation that could cause jitter in the switching waveform.
3) Inductor current is sensed during OFF time, when the low side FET is turned on, This makes it very convenient to sense this current by simply measuing voltage across the device.
what's the advantage (if any) of using the peak current mode then?
1) Early detection: In the traditional peak current mode control, the actual inductor current signal is fed into the loop. Hence, if the change is current is detectable immediately.
2) Current Sensing: The architecture relies on the inductor current being fed back into the loop to terminate the ON time. Hence, a minimum ON time is required. Shorter this time, wider the duty-cycle range. It is desirable to keep the minimum ON time as short as possible, but there are challenges associated with achieving that. One, the inductor current signal is very small and hence it needs to be amplified before feeding back into the control loop. The current sense amplifier has to not only amplify the signal, but also has to do so fast and the signal has to settle down quickly as well to be a viable signal. Second, the inductor current signal is detected by either sensing the voltage across the high side MOSFET (in synchronous buck regulator) or across the output inductor DCR (DC resistance) or across a current sense resistor in series with the inductor. In any of these current sensing methods, the current sense amplifier has to be able to detect a tiny differential signal with a very large common-mode signal. Makes the current sense amplifier design challenging.
3) Duty Cycle: Because of minimum ON time restriction, peak current mode controller is not suitable for the applications requiring a very small duty cycle (most such controllers in the market are specified at 100ns minimum ON time). On the other hand, this type of controller is very good for the applications requiring high duty-cycle.
The emulated peak current architecture described in another post, is very good for low duty cycle applications because the current sensing is done during OFF time. Hence, it simplifies the current sense amplifier design. However, the limitation there is the high duty-cycle applications.
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