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AD9739 Mu Phase Setting

Question asked by evandavis on Oct 8, 2015
Latest reply on Oct 16, 2015 by evandavis

I am using the AD9739 at a sample rate of 1.0 Gsps and the mu controller is failing to lock using the recommended SPI initialization sequence in Table 31 of the datasheet (failing step 14).  The issue is only on one of the boards I am testing, the other passes step 14 every time without issue.  The only changes I am making to the initialization are on step 8 (writing 0x45 to address 0x27) and steps 11 and 12 (writing 0x42 and 0x43 respectively to address 0x26).  This was done to match the target mu slope and phase settings of +5 from Table 28 for a 1.0 Gsps clock.

 

Looking at Figure 50 in the datasheet and trying to predict what it would look like at 1.0 Gsps, it would seem a value of +5 might not be able to map to any delay line tap value.  I tried changing the target mu slope to +6 the mu controller locks every time without issue.  Is there going to be some loss in performance caused by setting this to +6 instead of +5?

 

I also see occasional failures on the RX data lock but these are on both boards and seem much more random.  It will pass the majority of the time and then suddenly not pass a few times.  Not sure if this is typical behavior or a symptom of a bigger problem.  What would be a potential cause for the RX data failing to lock?  Are there any register settings that can be tweaked to get this to pass more consistently?

 

Thanks,

Evan

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