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I delay in fmcomms2 design

Question asked by rgetz Employee on Oct 8, 2015
Latest reply on Oct 8, 2015 by rejeesh

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In the Analog Devices evaluation FPGA image the receive data path into the FPGA uses the IDELAY components on each of the data pins and framing strobe.  It appears that the IDELAY components are configured dynamically through a control bus since we don’t see any fixed values listed in the hdl code or constraints file.  I was wondering if Analog Devices could provide us with the tap delay values that were being programmed into each IDELAY.