ref_clk input of AD9915 is 40Mhz.
When PLL is enabled,I expect the sysclk to be 2480MHz = 40MHz*31*2( FeedBack Divide N 0x1F).
However, signal from pin sync_out is about 17.24Mhz, as figure shown below. It means that sysclk is 17.24Mhz*384=6620.16Mhz? I don`t know what`s wrong with my AD9915....
CFR1 = SINE_OP|EXT_PDWN;
CFR2 = SYNC_CLK_EN|SYNC_OUT_EN|SYNC_IOMUX_EN;
CFR3 = LCK_DTCT_EN|PLL_EN;