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TRU not working for BF707

Question asked by Vince on Oct 6, 2015
Latest reply on Oct 7, 2015 by Vince

Hi there:

I tried a project using BF707 to read AD7606 at full sampling rate of 200ksps.

I used BF707 ez-kit (Rev. 1.0, with BF707-ENG on it) connecting to EVAL-AD7606 with wires.

I configured SPORT0A and DMA0 to receive the data and PortC03 as the input of the BUSY signal from AD7606.

 

Upon detecting the falling edge of PC3/BUSY, an interrupt service routine should be entered and inside SPORT0A would be enabled, while TRU is configured to pass the trigger of PortC03 to enable DMA0.

 

However, what it really goes is the interrupt is serviced and SPORT0A starts running, but DMA0 keeps waiting for the trigger that should be already fired off. As a result the DMA FIFO is fed up but the DMA does not transfer a bit. It just looks like the TRU is not functioning at all despite the registers are written into.

 

I did the configurations of DMA, TRU, and PINT much like in the examples of "EE-360 Utilizing the Trigger Routing Unit for System Level Synchronization".

 

In addition, I tried it on a customized board of BF607 + multiple AD7606 with almost the same configurations, and everything (TRU, PINT, DMA, and SPORT) worked well. Hence the SPORT part should be well configured for the BF707 ez-kit too.

 

Could anyone give me some advice as to what could cause this problem, given the fact that it could work on BF607 with almost the same configurations?

Thanks!

 

My DMA0 setting:

*pREG_DMA0_CFG = ENUM_DMA_CFG_ADDR2D |\

ENUM_DMA_CFG_TOV_DIS |\

ENUM_DMA_CFG_YCNT_TRIG |\

ENUM_DMA_CFG_NO_INT |\

ENUM_DMA_CFG_TRGWAIT |\

ENUM_DMA_CFG_AUTO |\

ENUM_DMA_CFG_MSIZE02 |\

ENUM_DMA_CFG_PSIZE02 |\

ENUM_DMA_CFG_SYNC |\

ENUM_DMA_CFG_EN |\

ENUM_DMA_CFG_WRITE;

 

My TRU settings:

*pREG_TRU0_GCTL = BITM_TRU_GCTL_RESET;

ssync();

// global control enable

*pREG_TRU0_GCTL |= BITM_TRU_GCTL_EN;

// trigger slaves asserted by BUSY interrupt

*pREG_TRU0_SSR14 = TRGM_PINT1_BLOCK; //SPORT0A

 

PINT1 settings:

*pREG_PORTC_FER_CLR = ADI_GPIO_PIN_3;

*pREG_PORTC_DIR_CLR = ADI_GPIO_PIN_3;

*pREG_PORTC_INEN_SET = ADI_GPIO_PIN_3;

*pREG_PORTC_DATA_CLR = ADI_GPIO_PIN_3;

 

adi_int_InstallHandler(INTR_PINT1_BLOCK, (ADI_INT_HANDLER_PTR)GPIO_handler, NULL, true);

 

*pREG_PINT1_EDGE_SET = ADI_GPIO_INT_PIN_3;

*pREG_PINT1_INV_SET = ADI_GPIO_INT_PIN_3;

*pREG_PINT1_MSK_SET = ADI_GPIO_INT_PIN_3;

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