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AD9608 Interleaved Data Output Timing

Question asked by damihuang on Oct 6, 2015
Latest reply on Oct 6, 2015 by DougI

Hi,

 

I think the datasheet of AD9608 made a mistake on the digital output timing of CMOS interleave mode:

 

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If the interleave mode is really working as above, how could it be helpful to reduce pin count? That I will lost CHA N-15, N-13, N-11,etc if only route CHA DOUT to FPGA?

 

The AD9204's datasheet maybe the right timing:

 

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Pls double check. Thanks.

 

Frank

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