I think the datasheet of AD9608 made a mistake on the digital output timing of CMOS interleave mode:
If the interleave mode is really working as above, how could it be helpful to reduce pin count? That I will lost CHA N-15, N-13, N-11,etc if only route CHA DOUT to FPGA?
The AD9204's datasheet maybe the right timing:
Pls double check. Thanks.