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AD9154 SERDES PLL not locking

Question asked by DZF on Oct 6, 2015
Latest reply on Oct 19, 2015 by Biao.H

I have a board that uses the AD9154 DAC, and I've been having trouble trying to set up the SERDES PLL. I have a reference clock input of 76MHz, and have the DAC PLL set up so that the VCO is running at 9728 MHz with a DAC clock of 1216 MHz. The DAC PLL is consistently locking without any issues (register 0x084 reads back 0x22).

 

When I try to configure the SERDES PLL, though, it is consistently failing to lock, and the SPI_CP_OVER_RANGE_LOW_RB bit is set in register 0x281 (this register is reading back 0x1A). I am writing 0x08 to register 0x230 and 0x05 to register 0x289 in order to select Full Rate Mode as shown in Tables 37 and 38 in the datasheet.

 

I've tried recalibrating by clearing and then resetting bit 2 of register 0x280, but after doing so I still read back the same value from register 0x281 (0x1A) indicating that the PLL is not locked.

 

Is there anything else I should need to do outside of the writes given in Table 21 in order to get the SERDES PLL up and running? Does it require the SYSREF input to be active in order to lock? I don't yet have a SYSREF source running on this board.

 

I am planning to run with 8x interpolation with one JESD204B lane per converter, so I expect the data rate to be 3.04 Gbps. The JESD204B transport layer settings are set up for Mode 2 using the settings given in Table 49.

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