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DDS AD9832  FSYNC line logic and timing

Question asked by PhilipLehman on Oct 6, 2015
Latest reply on Oct 6, 2015 by LouijieC

Hi All;


I actually have a pretty simple issue/question.  I have a design using the AD9832.  It work very well and performs (mostly) as desired...


EXCEPT,  occasionally the frequency output seems to glitch or shift slightly.   Does anyone have any similar experience with this behavior?   The software/microcontroller in my application updates the frequency continuously via the SCI interface.  Also, the system requirements are that the AD9832 frequency output is continuous and "smooth" when transitioning from one frequency to the next. 


When the frequency output is static, that is, the microcontroller is commanding the same frequency over and over again, the AD9832 output is rock solid.  No noticeable glitches.  The frequency discontinuity occurs only when the frequency output is in transition.  either to a higher or lower frequency.   I'm running the SPI interface at 500,000 kbps which should have lots of margin. 


Since the AD9832 is the only device on the SPI interface, we hold the FSYNC line low all the time.  it is not toggled between 16 bit frames.  Is this a possible issue  or should I be considering something else?


Thanks in advance for your help and input.