I simply want to connect an AD7980 to an Altera FPGA.
The AD7980 is set in CS\ mode 3 wires with (or without, both methods tested) busy indicator.
Everything looks perfect, except when the input voltage reaches some specific values corresponding to a count around 15292.
Ref and VDD are set to 2.5V. The + input is connected through a pot on VDD (- input to GND).
I can check the reading on SDO with an oscilloscope and also on a USB connection on the FPGA.
The values appear normal (a little noisy around an average value that changes when rotating the pot) except when reaching the area mentioned above: no other value than 15292 between 11242 and 15292 when turning the pot, as a switch in the SAR would be stuck or broken. This is also confirmed looking at SDO on the scope: the LSBs are toggling at all positions of the pot, except when in taht specific area, where the data sent by the ADC is absolutely stable corresponding to 15292.
I thought the ADC might have been damaged for any reason, I decided to use another one...
Exact same result except that the value is 15294 in that case.
At the first attempts, the Conv signal staid high for a very short time (about 20 ns, but probably affected by the current assembly on a breadboard with wires between the FPGA and the ADC), I tried increasing it to 100 ns and even used the No Busy indicator mode, with a µs delay... still the same.
The ADC is used at 100 KSPS with a data transfer rate of a little more than 1MBS (since our assembly is not that "clean" I didn't want to go up o the limits of performance of the ADC)
I'm sure the problem is on our side (otherwise nobody would have used this ADC!!!) but I can't figure out where.
With a 2.5V ref, the problem occurs between roughly 1.68V and 1.84V which is consistent with the value read 0x3BBE
Thanks for any advice