I have a design where I am using the ADV212 with a 16 bit host interface with a Freescale Kinetis K10 processor, using Freescale's "FlexBus" architecture. There are some differences, and while I obviously connected the address lines and data lines of the K10 to the ADV212 as expected, I am seeing issue reading direct registers, and writes to the ADV212 direct registers do not appear to work at all. What is puzzling is that SOME direct registers such as PLL_HI, MMODE, BUSMODE read back with what I expect as the power up default (0x88), but registers such as PLL_LO and a few others do *NOT* read back what the ADV212 user guide indicates should be the defaults on reset. For example PLL_LO should be 0x03 at reset, but I am seeing 0x00. So I have a few questions.
1. Are the reset defaults described in the ADV212 programming guide for the registers that have defined reset values in fact accurate?
2. Do the read and write operations REQUIRE a low going then high going pulse on the ADV212 RE and WE signals? I.e. does the ADV212 use the rising edge of WE to latch the write data into the register?
In my design, I connected the signals from the K10 to the ADV212 as follows:
FB_CS -> ADV212 CS
FB_OE -> ADV212 RE
FB_RW -> ADV212 WE
What this means is that the chip select, as expected, goes low during the bus cycle from the processor. The Output Enable timing on the K10 also appears to match what is expected for the RE signal on the ADV212, but the fact that I am seeing a difference in some of the expected register default values has me concerned about timing. Note I have run the bus clock for the processor all the way from 48MHz down to 6MHz, added many wait states, and other things, and see no difference in data read back performance.
Where I *THINK* I have an issue is in writing the ADV212. I misunderstood the Kinetis documentation and while their timing diagrams make it look like their "R/W" signal strobes low during a write cycle, it actually STAYS low until you decide to read the bus again. So it goes low at the beginning of the bus cycle, and never goes high as expected by the ADV212 timing diagram. This is why I believe I fail to latch data into the direct registers of the ADV212. My thoughts on how to salvage the situation are to use an OR gate to OR the CS and RW outputs of the Kinetis in order to generate a WE pulse for the ADV212, but use of such a gate may delay the rising edge of WE up to 2.5ns beyond the rising edge of CS, unless I also buffer CS to the ADV212.
Any recommendations and insight is appreciated. I have just a few days to work through this, and get a revised PCB into the production cycle. Everything on the PCB is working EXCEPT the bus interface to the ADV212 at this point. Schematic is attached.