I am using JESD204B DAC (983.04MHz interpolation x8, BB signal @122.88MHz) and ADC (245.76MHz) clocked by AD9528.
For MIMO purpose, I need to synchronize 2 boards.
Ref CLK is shared to both AD9528 from the FPGA.
From SYSREF_IN, can I be sure that the CLK/SYSREF for DAC/ADC will be aligned without causing a 1 cycle difference?
Thanks a lot.