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AD9957 IQ modulation timing needs

Question asked by lostinspacebar on Oct 1, 2015
Latest reply on Oct 6, 2015 by KennyG



I'm trying to verify my understanding of IQ modulation with the AD9957. My output frequency is in the 200MHz range so my SYS_CLK is currently set to 420MHz. Assuming I set the interpolation factor rate to 63, my PDCLK frequency is 3.333MHz.


1. This means, my host processor has to be able to detect an edge and change my 18 pins on the data port to an I and Q value (alternating between PDCLK cycles) before the next edge arrives. For 3.333MHz, this means I have about 300 nanoseconds to figure out the next I or Q value and set it on the 18-bit port. Is this correct?

2. My current host processor is a simple dsPIC running at 40MHz. I used to use profile switching to perform phase modulation but am I right in saying that it's impossible for the dsPIC to be able to perform IQ modulation since I only have about 300 nanoseconds between edges which translates to about 10 cycles on the dsPIC (I can't set 18 pins along with data retrieval in 10 cycles)?

3. There is a blackfin mode that allows you to serially clock in data for I and Q so it would only be 2 bits per edge. This is still not possible for my 40MHz dsPIC but am I understanding that correctly? Instead of 18-pins per edge for an I or Q, I'd be sending 1 bit of I and Q per edge using two pins.

4. I plan to overcome some of this using a faster processor but the eval board has a FIFO which seems like an interesting idea. If I had a large enough FIFO, could I just load it and have it dump data onto the IQ port clocked by PDCLK? Is there any reason this wouldn't work?