I am using an ADAU1442 in TDM4 mode (not packed) and have several questions:
1) Do settings of Serial Input Port Modes [9:3] (BCK pol, LRCK pol,... I2S, bit delay, Left Just...) affect TDM operation?
If so which bits impact TDM4 operation.
2) In TDM4 operation does the position of the LRCK rising edge matter? Note that in figure 25 it does ot align with the Slot 4/5 boundry.
3) I want to use an asynchronous BCLK in TDM4 mode which is greater than 128*LRCK. Can I just put out LRCK down edge, and 128 BCK cycles with 128 data bits (24 bits active 8 bits fill 24 bits active 8 bits fill 24 bits active 8 bits fill..) untill 4 channels of data are input, (or 129 cycles if I2S/Left Justified cannot be selected see 1) above). Or should I output 64 bits of data, wait for LRCK up edge then another 64 bits of data.
I find the data sheet inadequate in this area, is there a better reference?
Thanks in advance for any answer.