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ad9520 PLL lock problems

Question asked by markus on Apr 28, 2011
Latest reply on May 2, 2011 by LucaV

Hi, we're encountering problems setting up the PLL of a 9520-3 properly. As reference clock, a TCXO with fref=20MHz is used which directly drives the PFD. The 2GHz VCO is divided to 20MHz via a 32x-Prescaler, a B-Counter of 3 and an A-Counter of 4 (P=32, B=3, A=4)  which should yield an overall ratio of 100.

The problem: When selecting DLD (act. high) on the status-pin, we can observe a constant pwm signal but no steady digital lock.

Signals in the R and N branches are of the same frequency and shape.

The question: is this problem likely to be caused by the external loop filter? (since we changed the external filter several times (according to ADISimClk)).

 

Thanks in advance!

Markus Glitzner

 

P.S.: at the moment we attached a large cap between CP and BYPASS in order to observe the calibration of the VCO in addition to a filter 2nd order with 100pF || (1.43k -- 1nF) between CP and BYPASS.

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