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Getting strange result from reading the SPORT receive buffer.

Question asked by col on Apr 28, 2011
Latest reply on May 9, 2011 by Mitesh

I'm getting strange result from reading the SPORT receive buffer and hoping someone here can help me figure out what I did wrong.  I'm using the ADSP-21479 eval kit.  I connected SPORT0 to SPI0 where it is the master (transmitter and supply clock, frame sync (cs) and data) to SPORT0 which is the slave (receiver.)  Here is how I configured the SPORT0:

 

//Clear out SPORT 0/1 registers
*pSPMCTL0 = 0;
*pSPMCTL1 = 0;
*pSPMCTL2 = 0;
*pSPCTL0 = 0;
*pSPCTL1 = 0;

*pDIV0 = 0x00000000;  // Transmitter (SPORT0)
*pDIV1 = 0x00000000;  // Receiver (SPORT1)

 

*pSPCTL0 =  SLEN8|LFS|LAFS|CKRE|FSR;  

 

Here is low I configured the DAI pins for SPORT0.

SRU(DAI_PB01_O, SPORT0_CLK_I);  // CONNECT DAI_P01 PIN (INPUT) TO SPORT1 CLK
SRU2(LOW,DAI_PB01_I);
SRU2(LOW,DAI_PBEN01_I);        // disables DPI pin10 as input

SRU(DAI_PB02_O, SPORT0_FS_I);  // CONNECT DAI_P02 PIN (INPUT) TO SPORT1 FS
SRU2(LOW,DAI_PB02_I);
SRU2(LOW,DAI_PBEN02_I);        // disables DPI pin10 as input

SRU(DAI_PB03_O, SPORT0_DA_I);  // CONNECT DAI_P03 PIN (INPUT) TO SPORT1 DA
SRU2(LOW,DAI_PB03_I);
SRU2(LOW,DAI_PBEN03_I);        // disables DPI pin10 as input

 

Here is the code to read the SPORT0 receiver buffer.

while(1)
{
       spi_cmd_write(0xFA);
       if (((*pSPCTL0) & 0xC0000000) != 0)
             SPORT_RD_BUFFER = *pRXSP0A;
     
  Wait(10000);
}

 

SPORT0 (SPCTL0) is configured for 8-bit frame, frame sync required, late frame sync, active low framesync and rising clock edge for data frame sync sampling.  The captured waveforms of Framesync, SCLK, and data is posted in the attachments.  The captured waveforms look very similiar to the waveforms on page 486 (10-28) of the ADSP-214xx SHARC Processor Hardware Reference document except that my SPORT0 is initialized to use the rising edge of serial clock to sample framesync and data.  The strange thing with my code is SPI0 transmitted 0xFA and the SPORT0 received 0xF5 which is a barrel shift of 0xFA to the right by 1 bit.

 

Thanks you.

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