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ADN8831 external clock polarity and phase

Question asked by pskibinski on Sep 29, 2015
Latest reply on Oct 8, 2015 by ytu

Hello everyone,

 

I am developing a board with multiple power converters and need a synchronous out-of-phase operation.

 

Please clarify if the following statement is correct:

If an external clock source is connected to the device to SYNCI/SD pin, and PHASE pin is left floating, the high-side transistor (driven by SPGATE pin) will switch to ON state at the falling edge of the external clock.

In other words, a falling edge of the external clock marks the beginning of high current draw from VDD.

 

Thank you in advance,

 

Piotr

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