I am developing a board with multiple power converters and need a synchronous out-of-phase operation.
Please clarify if the following statement is correct:
If an external clock source is connected to the device to SYNCI/SD pin, and PHASE pin is left floating, the high-side transistor (driven by SPGATE pin) will switch to ON state at the falling edge of the external clock.
In other words, a falling edge of the external clock marks the beginning of high current draw from VDD.
Thank you in advance,