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AD9548 DPLL phase noise questions, please help

Question asked by Lester on Sep 29, 2015
Latest reply on Oct 5, 2015 by JLKeip



  I am testing the AD9548 output phase noise under free run mode.


  The testing set up is:

  AD9548 evaluation kit + 10MHz OCXO clock input

  output : 10MHz CMOS output at output 1. DPLL frequency set to 80MHz.


  The testing result :

  1. Only measure the 10MHz OCXO, the phase noise is -150dBc/Hz@1KHz, -160dBc/Hz@10KHz , -165dBc/Hz@100KHz, -167dBc/Hz@1MHz.


  2. AD9548 + OCXO at free run mode, set the DPLL frequency at 80MHz, no reference input.  The 10MHz output phase noise :  -140dBc/Hz@1KHz, -144dBc/Hz@10KHz, --141.4dBc/Hz@100KHz, -163dBc/Hz@1MHz


  You also can see the attached picture, the red line is original OCXO, the blue line is AD9548 output.


  I try different OCXO input configuration, OCXO changed to 1.8Vpp at SYSCLKN,  OCXO to SYSCLKP wich 0.1uF couple cap, and OCXO to J15, pass the ETC1-1-13 balun to the SYSCLKP.

  But all clock input configuration get the same result, the phase noise worse between 1KHz and 100KHz.



  What problem could course this phase noise problem?

  I also separated the AD9548 and OCXO power supply, use battery or switch mode supply, the phase noise just no any improvement.