I have 3 questions:
1) In the datasheet section "programming modes" it states that several registers are double-buffered and require a write to register 0 for the new values to take effect. Then it states "Register 6 is also double buffered, but only if DB14 of Register 4 is high."
It is true that double buffering is only controlled for register 6? I was under the impression that DB14 of register 4 would control double buffering for all registers.
2) I noticed that the evaluation board always uses the initialization sequence for programming the registers when changing frequencies. And the SPI bus on the eval board runs at a relatively low clock speed (approx. 500kHz I think). Our SPI bus is running much quicker.
With that in mind, and assuming that the registers 0,1,2,4 need to be double buffered, how important is the wait (16 ADC_CLK cycles) between writing register 4 and register 0 (shown in the frequency update sequence)? What happens if register 0 gets programmed sooner?
If the initialization sequence is always used to change the frequency, does that wait time still need to be there?
3) In the datasheet "frequency update sequence", how important is toggling DB4 in register 4 (counter reset enable)? What happens if it is not toggled? If the initialization sequence is used to change the frequency does DB4 still need to be toggled?