I am trying to use an FPGA to control an AD9910 evaluation card to generate single tone signals and implement an AWG via the parallel modulation. I noticed that AD9910's single tone mode is different from AD9959, which I used to work with. I put down a list of steps to achieve the functions. Would someone with experience tell me whether it is correct?
The AD9910 evaluation card will take an external 1GHz clock as the reference. The internal PLL will be bypassed.
0. Assert the MASTER_RESET to reset the chip.
For single tone mode:
1. initialization: write to CFR2 to enable amplitude scale from single tone profile.
2. Set the profile pins to 3'b1;
3. Write to single tone profile 0 register with freq, amp and phs.
4. Set the profile pins to 3'b0 to update the profile register.
Further operations will skip step 1.
(Is it necessary to change the profile pins every time I change the profile register's content?)
For parallel modulation, assuming that the board is already in the single tone mode.
1. Initialization: write to CFR2 to
Set data assembler to hold the last values.
Enable the parallel port.
Set FM gain.
2. Write to FTW to set the base frequency. (Or I should use the profile register to set the base frequency?)
3. Use the parallel port and TxEnable to change the freq, amp and phs ...
The last steps will set all the modulations to zero.
4. Finalization: write to CFR2 to fall back to single tone mode.
Disable parallel port.
Enable amplitude scale from single tone profile.
Further single tone operations will start from its step 2, and parallel modulation from its step 1.
Are these sequences correct? Do I miss certain steps?