CrossCore Embedded Studio 2.1.0 C/C++ Compiler and Library Manual for SHARC Processors says that Interrupt Handler Pragmas are not supported for SHARC+ processors.
Does support Interrupt Handler Pragmas for SHARC+ processors come in future?
I don't believe so, but I will check with the developers to find out. The reason it is not offered on the new SHARC+ processors is because the infrastructure for interrupt handling changed significantly between the two generations. The SHARC+ processors do not have a jump table like the older SHARC cores did, where interrupt pragmas were required to ensure that C developers got the proper assembly wrap code to preserve context and return for functions identified to be ISRs. Instead, the new SHARC+ core receives a single interrupt at a dedicated interrupt level that is reserved by the System Event Controller (SEC). The SEC is fully programmable by software to prioritize any interrupt source ID, but hardware handles everything at the system level using the single interrupt-level set to be self-nesting in nature (to allow for higher-priority interrupts to come in and interrupt the current interrupt).
Basically, a single SEC interrupt handler is pre-written and comes with CCES...this SEC dispatcher includes all the wrap code needed to protect context and properly return, as well as perform the required handshaking with the SEC to indicate completion of service on a specific interrupt source ID. All the user needs to do is associate a function with the source ID using the SEC device driver, which logs to a look-up table that the SEC dispatcher uses to identify the vector to take (which is now just a sub-routine) when a specific source ID comes in.
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