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ADV7511 w/ SSC Input Clock

Question asked by matto_jt on Sep 24, 2015
Latest reply on Oct 9, 2015 by DaveD



Our Zynq FPGA based system employs ADV7511 for driving video output HDMI interface.   The interface between FPGA and ADV7511 is LVCMOSS33, and we've found that this single-ended interface is the source of significant of EMI in our system.   In an effort to reduce EMI, we've added SSC on the FPGA Video Clock which internally clocks the parallel video interface and I/O to the ADV7511.  With this change enabled, we've found it yields significant reduction in EMI.  However, we also notice that with SSC enabled on the FPGA Video Clock, we no longer sync with a number of monitors, and fail to sync at resolutions higher than 1080p.  (Previously w/o SSC enabled in FPGA, we interfaced and sync'd fine with monitors up to 1920x1200.)

We've reduced the spreading to as low as the FPGA MMCM circuit can support - 25khz modulation bandwidth - and with that setting, we still see the problem (and the reduction in EMI). 

With SSC enabled, we've also noticed that PLL Lock in ADV7511 remains active, suggesting that the spreading is not causing the internal PLL to fail to lock.

We've also tried lowering the drive strength and slew rate of the FPGA I/O, and we found 8mA, FAST on the LVCMOS33 I/O was the lowest limits we could reach without showing any video artifacts.


I've reviewed the ADV7511 programming guide, and it mentioned a variety of ways of syncing, including generated syncs.  We are currently using the input sync sources, but could change this approach if it would help.  Perhaps the generated syncs would have better performance, since they would be derived from internally sourced clock.


Would using generated syncs help here, or perhaps some other ADV7511 configuration option to help with our system?


Thanks in advance,