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Issues using fcomms1 on ZC706

Question asked by McG on Sep 24, 2015
Latest reply on Sep 30, 2015 by rejeesh

Hi all,

I have a system composed by ad-fcomms1-ebz and Xilinx ZC706.

20150924_183434.jpg

 

In order to test the system I used, for the hardware, the hdl-master taken here analogdevicesinc/hdl · GitHub and, for the software, the no-OS packages found here analogdevicesinc/no-OS · GitHub.

 

Using Vivado 2014.4.1 under linux os, for hdl I built the system without problems using the shell command:

 

>> make fmcomms1.zc706

 

For the software, I used the main.c contained in the no-OS/fmcomms1/Common. The compilation was ok both for hardware and software.

The problem is the in the plot of signals coming from ADC and stored in the ILA.

 

ila_adc.PNG

1. Why the probe1 is composed by 64-bits while the ADC should generate 4 14-bits sine waves (as shown here: AD-FMCOMMS1-EBZ Quick Start Guide on Xilinx FPGA Boards Without OS [Analog Devices Wiki])?

3.PNG

 

 

2. Deleting the bit 15 and 16 of each 16-bits group I obtain the followig result:

1.PNG

 

If I magnify the details obtain:

2.PNG

 

The configuration of signal representation is signed. I didn't change anything both for hardware and software original settings (I changed just the receiver gain with 1). So I don't know why I obtain this behaviour. The consolle output of SDK is the following:

 

Running XCOMM Test Program

 

Initializing XCOMM I2C...

XCOMM Init I2C OK!

 

Getting XCOMM Revision...

Board Version: Analog Devices, FMC Comms 1, 01009, AD-FMCOMMS1-EBZ, PCB Rev.C, BOM Rev.0

 

Initializing XCOMM Components...

XCOMM Init OK!

 

Initializing the Rx path...

XCOMM Rx Init OK!

 

Initializing the Tx path...

XCOMM Tx Init OK!

 

ADC sampling rate [Hz]: 122880000

 

DAC sampling rate [Hz]: 122880000

 

DAC available interpolation frequencies [Hz]: 122880000 245760000 491520000 983040000

 

DAC available center shift frequencies [Hz]: 0

 

Testing the ADC communication...

adc_test: adc_clock(122.880MHz)

adc_test: mode( 1), format( 1)

adc_test: adc_clock(122.880MHz)

adc_test: mode( 2), format( 1)

adc_test: adc_clock(122.880MHz)

adc_test: mode( 3), format( 1)

adc_test: adc_clock(122.880MHz)

adc_test: mode( 4), format( 1)

adc_test: adc_clock(122.880MHz)

adc_test: mode( 5), format( 1)

adc_test: adc_clock(122.880MHz)

adc_test: mode( 6), format( 1)

adc_test: adc_clock(122.880MHz)

adc_test: mode( 7), format( 1)

ADC test complete.

 

Testing the DAC communication...

dac_setup: dac_clock(122.882MHz)

dac_sed: s0(0x0000AAAA), s1(0x00000000)

dac_sed: s0(0x00005555), s1(0x00000000)

dac_sed: s0(0xAAAA0000), s1(0x00000000)

dac_sed: s0(0x55550000), s1(0x00000000)

dac_sed: s0(0x00000000), s1(0x0000AAAA)

dac_sed: s0(0x00000000), s1(0x00005555)

dac_sed: s0(0x00000000), s1(0xAAAA0000)

dac_sed: s0(0x00000000), s1(0x55550000)

dac_sed: s0(0x00000000), s1(0x00000000)

dac_sed: s0(0xAAAAAAAA), s1(0x55555555)

dac_sed: s0(0x55555555), s1(0xAAAAAAAA)

DAC test complete.

 

Setting the VGA gain to: 0.1 dB

Actual set VGA gain: 4.500 dB

 

Setting the Rx frequency to: 0002400

Actual set Rx frequency: 0002400

 

Setting the Tx frequency to: 0002400

Actual set Tx frequency: 0002400

 

Setting up the DDS...

DDS setup complete.

 

Reading data from air...

Read data from air complete.

 

Finished XCOMM Test Program

 

 

Regards

 

RF

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