There is a rather good FAQ for the BF70x on this subject FAQ: How can I initialize DDR memory device connected to BF70x processor ? but I can't see an equivalent for the BF60x?
So I am trying to fill the gaps, I am looking at the ADSP-BF609-resets.xml provided with CCES 2.0.0 in C:\Analog Devices\CrossCore Embedded Studio 2.0.0\System\ArchDef (when CCES is installed in the default location!). Can I assume that this has been written from the DDR2 fitted to the BF609 EZ BOARD? The ADSP-BF609 EZ-KIT Lite Evaluation System Manual (1-12) suggests the BF609 EZ BOARD has a 128 MB Micron MT47H64M16HR-3. Looking at the data sheet for this DDR2 I can see for the -3 part the CL is 5 ... but decoding the CL set in the ADSP-BF609-resets.xml I get 4 ... any ideas where I am going wrong?
Then there is the code example in the EZ BOARD example POST DDR2 test. Again in ddr_test.c the CLis set to 4 if the DDR clock is 200 MHz or more, CL is set to 3 if the DDR clock is less than 200 MHz.
This doesn't stack up, something is wrong here ... any assistance appreciated!