What usually limits the SFDR performance of a high speed DAC? What can I do to improve the SFDR performance in my design?
There are typically two types of spurs at the output of a high speed DAC, DAC harmonics and digital related spurs.
DAC harmonics are the harmonic contents of the DAC output signal due to data-dependant nonlinearity. They are located at n*Fout and Fdac-n*Fout on the output spectrum. Here Fout is the DAC output frequency and Fdac is the DAC clock frequency.
The other type of spurs is related to the digital circuitry in a DAC. Due to the functionality (ie interpolation and modulation) and implementation (multi-path design), the digital circuitry in a DAC usually runs at the frequencies that are sub-multiples of the Fdac. Some of the energy at these slower speeds gets coupled to the analog portion, through on-chip and/or off-chip paths. This coupled energy eventually shows up at the DAC output as spurs located at m*Fdigital +/- n*Fout. Fdigital is the frequency DAC digital circuitry runs at.
A few suggestions for improving the SFDR performance in a design.
1. Choose a good frequency plan.
Good frequency planning allows harmonics and digital related spurs to fall out of the band of interest.
2. Choose a clean path for the DAC clock.
Anything coupled onto the DAC clock gets mixed with the output and shows up as spurs at the DAC output. A path that is reasonably isolated from digital circuitry and other clock paths on a PCB should be picked for the DAC clock.
3. Sufficient and effective decoupling at the supply pins
Supplies especially clock supplies are the most vulnerable paths to the digital related spurs. Good supply decoupling techniques minimize the chances of coupling digital energy to the analog circuitry.
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