I have tumbled across the following problem which I don't know how to solve.
When I use the AD9910 DRG mode to frequency sweep from 10 MHz to 100 MHz,I need the sweep complete in 1 ms, and shut down DRG output temporarily sustained 4 ms.Then repeat the over process(5ms per period).
I use no-Dwell high ramp generation. I send a trigger pulse via DRCTL pin per 5 ms.
A MCU monitoring the DROVER pin and detecting voltage level rise, then trigger a rising interrupt(if rising detected). In the interrupt service routine, I disable DRG with setting CFR2 bit =0 plus I/O Updta when DROVER turn into 1 from 0 which indicate the completion of sweep. And before the next effective DRCTL pulse, I enable the DRG with setting CRF2 bit=1 plus I/O update.
I found the following unexpected behavior, the sweep time badly less 1 ms after I disable/enable DRG according to DROVER signal.
Two figures attached, the normal.png is do nothing with DROVER singal. And abnormal.png is my problem, the sweep time is not equal 1ms, but 1ms is expected.
Is it possible to disable/enable DRG with configuration CFR2 bit periodly? Or are there other ways to solve this problem？