AnsweredAssumed Answered

AD9266 clock divider problems

Question asked by sinclairrf on Sep 19, 2015
Latest reply on Sep 22, 2015 by DougI

I'm driving several AD9266-20 ADCs with a common 80 MHz clock and using the internal clock divider to sample signals at 10 MHz.

 

The problem is that histograms of the ADC samples look more like 2-bit or 4-bit ADCs than a 16-bit ADC for a half-scale input sine wave.  If I reduce the clock division ratio and sample at 20 MHz, I get another couple of good bits.  Similarly, if I "over clock" the 20 MHz speed grade part and sample at 40 MHz, I get even more good bits -- the number of good bits being depending on which of the ADCs I'm operating.  Sampling at 80 MHz with the 20 MHz speed grade parts has not worked.

 

Myself and another engineer have read the data sheet and AN-877 and can't find any secret settings that would make the ADCs sample correctly at 10 MHz, but I'm still suspicious that there's some little detail that we're just not seeing.

 

The following is a list of the 16-bit register addresses and the corresponding settings we're using for the device and to command the desired "divide by 8" clock operation.  The sample rate from the device is consistent with the external clock and the "divide by 8" setting.  We tested the I/O operation using various test patterns and they all worked, so we're confident we're sampling the received data correctly.

 

0x0008 0x03  // chip-wide digital reset

0x00FF 0x01  // transfer registers 8:end

0x0008 0x00  // chip run

0x0009 0x01  // enable DCS for divide ratios other than 1, 2, and 4

0x000B 0x07  // divide by 8

0x000D 0x00  // disable test mode

0x0010 0x00  // no offset

0x0014 0x81  // 1.8 V CMOS I/O, twos complement output

0x0017 0x27  // enable data delay of 4.48 ns (good channel:  3)

0x00FF 0x01  // transfer registers 8:end

Outcomes