I want to cascade one LDO from one of the buck in the ADP5022, will the switching noise of the buck affect the LDO performance?
It depends, if the voltage difference between the LDO input/output is at least 300mV the PSRR of the LDO will well suppress noise below 100-kHz, this can be generated by transients on the buck output or the buck operating in PSM. If the voltage difference is small or the LDO operates in dropout the PSRR will deteriorate to a point where the noise at the input goes to the output. Switching noise generated by the buck, when operating in PWM, will not be suppressed by the LDO control loop because of the limited amplifier bandwidth however the output capacitor together with the board parasitic can help to suppress the switching noise, please refer to the PSRR curves provided in the ADP5022 datasheet to estimate the suppression level around 3-MHz. In those cases it is required a high level of noise suppression it is recommended to add a LCR filter at the output of the LDO as shown in the attached figure, the resistor is needed to damp the resonance of the filter. Filter characteristic depends on the critical frequencies where the load circuit is particularly sensitive.
Can you give the design details of this Filter?Especially filter components calaculation and relation with ripple.
or a simple example ?
I want to use this as power supply for 16 bit ADC and a medium gain INAMP ? Usually I will not use a DC to DC to supply the ADC,Vref and INAMP.I will use a seperate LDO.
but do you think with your filter I can save on the seperate LDO and still I can get the same performance?
As requested I have attached a document showing the proposed filter implementation and design, please note that this filter was designed to be effective above 100kHz with minimal resonance and targeting space constrained applications (main target for the ADP5022). The document assumes that the intrinsic high PSRR of the LDO is able to suppress supply ripple at lower frequencies. You may need to fine tune the filter performance according to your needs, the document here attached contains the guidelines for the filter design but let me know if you need additional information
I understand from your reply that you would like to supply the ADC, Vref and INAMP directly from a switcher with a post filter, please note that the configuration suggested in this post is a switcher supplying the input of the LDO (Which is often the case for the ADP5022) and a filter placed after the LDO to suppress frequency above the MHz range where the LDO's PSSR is not much effective (This is common to LDO architectures due to the limited loop gain at higher frequencies).
It is indeed possible to power noise sensitive circuits with a switcher and I have added few links to ADI documents showing some examples and considerations. In order to provide a more precise answer I will need to know more about your application, in the meantime I would like to offer some simple guidelines:
Thanks for such a detail reply.
Pls allow me to study this, I will come back in one or two days.
Thanks once again !
I have simulated and tested the filter circuit and yes it works better.
The resistance helps to damp the over shoot in the transition region of the filter, I wonder can't we use a moderate ESR electrolyte that may serve both the purposes Capacitor and a resistor and cost saving.This is about the post LDO filter which you have mentioned.
I think for high speed ADCs the precision is low and even the ENOB is not high and hence it is quite ok to use the DC to DC directly.
My application is Low frequency close to DC signal level coming from Accelerometer, I need pretty good precision Model 1 min 14 bit and Model 2 min is 21 bits.So I am designing with LDO inserted in between the DC to DC.I think for low frequency design with high precision we can not use the DC to DC directly, what do you think?
I know that LDO rejects the Ripple and has a RRR and we are making use of that to stop the low frequency noise coming from DC to DC that can act as a noise floor to ADC and reduce the SNR.
Few doubts about this,now a days all DC to DC are being operated in the MHz range to optimize for the Inductor Size and efficiency, do they generate so much nosie in the Low frequency region?Can't we place such filters at the output of the DC to DC to make it low noise only in high frequency region easily?Or it might add ESR and reduce the regulation?this is just a thought !
What happens when there is overshoot in the Frequency response of a filter? does the noise in that region gets oscillated,resonated and amplified?
Basically how the LDO removes the noise,ultimately it is just a Linear Transistor and an error amplifier configuration?
And how the ADP2114 removes the strong noise contributed by the Buck architecture? usually on scope we used to see Noise in mV for other old DC to DC,some even gives noise if you place the probe physically over the inductor in the Air !!! Is there any special considerations done in the chip for Inductor cureent Ramp up?
Pls give your excellent expert opinions
In theory it is possible to replace the ceramic capacitor with an electrolytic type however there are few things you need to consider: It is true that you will have a higher ESR but also the ESL will be higher and the resonant frequency may occur at much lower frequency compared to ceramics therefore it is important to model the electrolytic capacitor with all its parasitic in order to verify that the filter operates as designed. Another issue to consider with the electrolytic capacitors is the wide tolerance and the effect across temperature, especially at low temp range. Unless you are really pressed with cost I would suggest to stay with a ceramic capacitor.
I agree with your assessment, high precision ADC requires special care and supplying directly from a DC/DC, even with a two stage filter, may not be enough, in this case the most efficient solution is to use a buck as pre-regulator supplying an LDO with a post-filter as the one suggested in this thread. When using an integrate device like the ADP5022 you need also to consider possible magnetic coupling from the inductor(s) to other nearby components, this is especially critical in space constrained application where the LDO post-filter may be placed close to the switcher. If your board is sufficiently large, it is better to place the post-filter close to the ADC. In addition you may consider to use true multilayer ceramic inductors to minimize the magnetic coupling as indicated previously.
If the filter is allowed to overshoot it can end up increasing the noise around the resonant frequency, if you circuit is particularly sensitive at these frequencies the filter may not help however if you choose the filter resonant frequency well below the critical area then the overshoot may not be an issue, just consider that frequencies around the filter resonance will be amplified.
It is true that in modern portable switchers the frequency had increased however since the internal switching frequency is generated by a RC oscillator some frequency jitter will occur, this jitter may show up at a lower frequency spectrum and can be affected by operating conditions (line and load transients, supply voltage etc.). If you have access to a spectrum analyzer you could probe the output of the DC/DC and after the LDO post-filter to see if the low frequency component can be critical in your system.
The two main sources of noise in an LDO are the thermal noise, mostly due to the amplifier, band-gap and to a second degrees resistors, you can refer to the noise curves (integrated and spectrum noise) to understand this type of noise, typically the lower the output voltage the lower is the noise. A second source of noise in an LDO is due to input voltage ripple that is not sufficiently suppressed by the control loop. High gain in the control loop improves the PSRR however since the amplifier has a limited bandwidth, frequencies above the cutoff frequency will not be properly suppressed, you can see this behavior by looking at the PSRR curves, you will also see that (in the ADP5022 case) the PSRR improves around 3MHz, this is due to the output cap and board parasitic that resonate around that point. You cannot rely too much on this phenomenon unless you are able to characterize your system, even in this case you need to make sure that capacitors and board parasitic will not change over time or with different components vendors.
The best way to measure switching noise with a scope is to use a very short ground and tip connection, we usually coil a wire around the scope ground jacket (you need to remove the insulator) so you can touch the two terminals of the capacitor under test. You can also reduce the scope bandwidth to 20MHz to eliminate higher harmonics (there is a debate whether you want to see the whole signal or just concentrate around the area of more concern, you can try both and see the difference), you also need to check the noise close to the supplied circuit using the same local probe tip, you will most likely see that the noise is much lower than close to the switcher, also make sure to use true multi-layer inductors as discussed before to minimize the magnetic coupling.
Hope this answer your questions, if not please do not hesitate to let me know. Thanks
From: ChaitanyaB firstname.lastname@example.org
Sent: Thursday, July 28, 2011 9:21 PM
To: Zecchini, Maurizio
Subject: New message: "LDO noise performance when cascaded from a buck in ADP5022"
Analog Devices EngineerZone<http://ez.analog.com/index.jspa>
LDO noise performance when cascaded from a buck in ADP5022
reply from ChaitanyaB<http://ez.analog.com/people/ChaitanyaB> in Power Management - View the full discussion<http://ez.analog.com/message/29595#29595
Retrieving data ...